Proto commits in NVIDIA/tensorflow

These commits are when the Protocol Buffers files have changed: (only the last 100 relevant commits are shown)

2021-09-13

Merge branch 'master-tf1-cuda_malloc_async_fixes' into 'master-tf1' [TF1] Fix cudaMallocAsync See merge request dl/tensorflow/tensorflow!605 (cherry picked from commit 68d8ef4ba479fe9ebf531a373a1003cf187c9a7c) 456352bd [Crash fix] Other part of TF need the stats for GPU allocator. 5988bca4 Add a cudaMallocAsync test 624d6d1f [Crash fix] Handle correctly the passed stream. bcdfad70 Use a static cast df76191f Make the new options experimental and add it to the golden list of public API. 56cdf5d7 Use the new option b7097a7d Variable/function renaming. Also make a counter atomic to be more future... 0afa4788 Fix cherry-pick

The documentation is generated from this commit.

Enable cudnn batchnorm based levels rather than bool Also squashes: Build failure fix Address Bas's comments Remaining changes Test changes

Updated hlo_to_llvm_ir to also emit PTX and re-enable tests using it. See merge request dl/tensorflow/tensorflow!555

XLA persistent compilation cache Store results of llvm->ptx and ptx->cubin compilations for subsquent executions. Also Squashes: Include ptxas options in hash when generating key for persisten cache fix botched TF2->TF1 integration

Integrate CUDNN frontend API for convolution Also squashes: Add cudnn_frontend patch and change macros Apply filter over fallback list and add winograd filter Remove redundant headers Add flags Add env var for cudnn frontend APIs Fix empty fallback lists

[skip ci] XLA enables BN+Act and BN+Add+Act fusion when implementing kBatchNormTraining HLOInstruction as cudnn custom call

XLA cudnn Softmax

[XLA/GPU] Size-constrained buffer allocation

Phase3 backport upstream XLA See MR 289. Squashes: Remove deprecated variants of DynamicSlice and DynamicUpdateSlice builders Remove the old tensorflow/compiler/{xla,mlir} directory Add the new XLA/MLIR directory Replace the LLVM/MLIR config directory Update LLVM version structure BUMP LLVM version Automatic fixup Disable new XLA call to not-present new MIOpen interface Change `LocalClient::Compile` to support returning multiple executables (one per partition). [TF2XLA] Preserve the dynamic dimension (-1) when building a reshape. [XLA] Respect set-dimension-size in dynamic dimension inference. Support fill op with (bounded) dynamic shape input. Add missing header file for the TF1/TF2 bridge. Better ptxutil TF1/TF2 bridge Add missing include Disable the same tests as what is disabled in gitlab/master Add another TF1/TF2 bridge header Update tests and HLO printing to be valid JSON. Disable tests that shouldn't be run in oss. Fix disabled tests handling Comment broken license include Fix missing call in TF1. Plumb exponential_average_factor through stream executor to cudnnBatchNormalizationForwardTraining and the equivalent ROCM function. Remove vestigial code from cuDNN 4 in stream executor. Manual fixup of FusedBatchNorm conflict TF1/TF2 Bridge. Add dummy function to respect the new API. Undo some change as new the TF1/TF2 bridge cover this. DISABLE non OSS tests. Disable a tests at the right place. [TF:XLA] Move XLA tests that depend on contrib in preparation for TF 2.0 [XLA] Split testParameterizedTruncatedNormalIsInRange to avoid timeout. Implement F64 scalar addition for XLA TPU backends. Implement F64 scalar multiplication for XLA TPU backends. [XLA] Add some F64 tests for MatMul. [XLA] Slightly change some test inputs/tolerances [XLA] Brings F64 error thresholds in rough accordance with F32 Add test for unstack op. Add test for Expm1 for small parameter regime of complex numbers. Annotate a test with tf_cuda_tests_tags(). Manual fixup. Run the test multiple time. This should trigger the compilation. Try more runs. Add Debug print to help debug in case of problem. Try to fix the test. Add a comment Fix checkpoint reading. The compression was disabled. Fix the copy bug. Add a test NFC: rename a variable [XLA] Extend the Algebraic Simplier to convert Pow(x, 3) -> x*x*x. This is faster.

[XLA] Backport a few missing PRs See MR 315. Cherry-picks upstream commits for: * vectorize row reduction for even row size * Extra VLOG for PTXAS calls Squashes: Merge pull request #38136 from nouiz:fbastien_xla_reduce_sm_v5_push_vec_rb2_manual_cherry-pick Better error message. Now we print part of the module name that caused the error, so it is easier to find the right file. Use EmitWriteArrayElement that add annotation. This could help LLVM to vectorize. add -DDEBUG_BUILD to dbg profile Backport PR: 39734, add an XLA_FLAGS parameter Add back a fix that was lost in the cherry-pick due to a change of order.

Create an TF1/TF2 internal bridge Phase2 MR for XLA backport. See MR 284. Squashes: Introduce new RngBitGenerator HLO Update blocking_counter setup to the upstream version. Add rules dynamic_annotations and mutex that exist upstream. Add define to the new TF name: TF_GUARDED_BY, PT_GUARDED_BY, TF_EXCLUSIVE_LOCKS_REQUIRED, TF_LOCKS_EXCLUDED Add rules for bfloat16 and numeric_types Backport some bazel rules: tf_exec_properties, tf_grpc_dependency and tf_grpc_cc_dependency Backport tensorflow/core/protobuf/tpu/compile_metadata.proto Add conversion file for asm_compiler Add build/include to convert between the new/old interface. Add new dependency platform_port, status and redzone_allocator. redzone Continue TF API bridge CompileGpuAsm Move all new bazel rules at the end of the file. Add a rules numbers at the new place. Add dlpack Bridge TF1/TF2 add an header. Fix some tests build Include the right dependency. Otherwise, it cause protobuf init error.

Adds new protobuf message HloExecutionProfileData, which describes HloExecutionProfile. PiperOrigin-RevId: 269313040

Backport PR: 39734, add an XLA_FLAGS parameter

Rename proto key to not conflict with upstream. Start our own range of IDS.

Add AsyncOut support for XLA. This speeds up the multi-gpu training with Horovod by asynchronously triggering the outputs of XLA clusters fed to the HorovodAllreduce nodes. The feature is currently off by default; turn it on by setting TF_XLA_FLAGS="--tf_xla_auto_jit=1 --tf_xla_async_io_level=1". Some data points on 8GPUs on DGX-1, XLA-Async vs. XLA-Sync (i.e., before this commit): 13% perf gain on BERT large pretrain squad fp32, BatchSize=2 7% perf gain on Unet medical trainbench fp32 Design Doc: https://docs.google.com/document/d/1oohJC3BgQYmCb0njAf1Iqd1MShg4cPSeu9ZelnOFY8c/edit Authors: Trent Lo and Ayan Moitra

Merge pull request #35621 from bas-aarts:bas_auto_tune_level PiperOrigin-RevId: 291051983 Change-Id: I9518cca1eb07e44be7857b0c3d87c94de420fdce

[XLA] add the Scatter option to not do atomic operation. This should keep the backward compatibility when this option didn't exist. Also squashes: Add a test for Scatter without atomics. Update comment Add documentation and tests change the new parameter name. Fix doc typo and add a test.

2021-05-20

XLA persistent compilation cache Store results of llvm->ptx and ptx->cubin compilations for subsquent executions.

2021-04-14

[no cache] Integrate CUDNN frontend API for convolution

[skip ci] XLA enables BN+Act and BN+Add+Act fusion when implementing kBatchNormTraining HLOInstruction as cudnn custom call

XLA cudnn Softmax

[XLA/GPU] Size-constrained buffer allocation

Backport PR: 39734, add an XLA_FLAGS parameter

Add the new XLA/MLIR directory

Remove the old tensorflow/compiler/{xla,mlir} directory

Backport tensorflow/core/protobuf/tpu/compile_metadata.proto

Introduce new RngBitGenerator HLO The new instruction has the same signature as xla::BitGeneratorTy what takes a key and a state and returns uniformly distributed random bits and a new value for the state. Its aim is to enable backend specific lowering for the various random bit generator algorithms what should unlock optimization opportunities. PiperOrigin-RevId: 293569472 Change-Id: I4f69d4f9858378fb1241435032ef75657933c056

Adds new protobuf message HloExecutionProfileData, which describes HloExecutionProfile. PiperOrigin-RevId: 269313040

Backport PR: 39734, add an XLA_FLAGS parameter

Rename proto key to not conflict with upstream.

Start our own range of IDS.

Add AsyncOut support for XLA. This speeds up the multi-gpu training with Horovod by asynchronously triggering the outputs of XLA clusters fed to the HorovodAllreduce nodes. The feature is currently off by default; turn it on by setting TF_XLA_FLAGS="--tf_xla_auto_jit=1 --tf_xla_async_io_level=1". Some data points on 8GPUs on DGX-1, XLA-Async vs. XLA-Sync (i.e., before this commit): 13% perf gain on BERT large pretrain squad fp32, BatchSize=2 7% perf gain on Unet medical trainbench fp32 Design Doc: https://docs.google.com/document/d/1oohJC3BgQYmCb0njAf1Iqd1MShg4cPSeu9ZelnOFY8c/edit Authors: Trent Lo and Ayan Moitra

Merge pull request #35621 from bas-aarts:bas_auto_tune_level PiperOrigin-RevId: 291051983 Change-Id: I9518cca1eb07e44be7857b0c3d87c94de420fdce

change the new parameter name.

[XLA] add the Scatter option to not do atomic operation. This should keep the backward compatibility when this option didn't exist.

2020-12-18

XLA cudnn Softmax

2020-11-23

[XLA/GPU] Size-constrained buffer allocation

2020-10-29

Adds new protobuf message HloExecutionProfileData, which describes HloExecutionProfile. PiperOrigin-RevId: 269313040

Backport PR: 39734, add an XLA_FLAGS parameter

Start our own range of IDS.

Rename proto key to not conflict with upstream.

Add AsyncOut support for XLA. This speeds up the multi-gpu training with Horovod by asynchronously triggering the outputs of XLA clusters fed to the HorovodAllreduce nodes. The feature is currently off by default; turn it on by setting TF_XLA_FLAGS="--tf_xla_auto_jit=1 --tf_xla_async_io_level=1". Some data points on 8GPUs on DGX-1, XLA-Async vs. XLA-Sync (i.e., before this commit): 13% perf gain on BERT large pretrain squad fp32, BatchSize=2 7% perf gain on Unet medical trainbench fp32 Design Doc: https://docs.google.com/document/d/1oohJC3BgQYmCb0njAf1Iqd1MShg4cPSeu9ZelnOFY8c/edit Authors: Trent Lo and Ayan Moitra

Merge pull request #35621 from bas-aarts:bas_auto_tune_level PiperOrigin-RevId: 291051983 Change-Id: I9518cca1eb07e44be7857b0c3d87c94de420fdce

change the new parameter name.

[XLA] add the Scatter option to not do atomic operation. This should keep the backward compatibility when this option didn't exist.

Backport PR: 39734, add an XLA_FLAGS parameter

Add the new XLA/MLIR directory

Remove the old tensorflow/compiler/{xla,mlir} directory

Backport tensorflow/core/protobuf/tpu/compile_metadata.proto

Introduce new RngBitGenerator HLO The new instruction has the same signature as xla::BitGeneratorTy what takes a key and a state and returns uniformly distributed random bits and a new value for the state. Its aim is to enable backend specific lowering for the various random bit generator algorithms what should unlock optimization opportunities. PiperOrigin-RevId: 293569472 Change-Id: I4f69d4f9858378fb1241435032ef75657933c056

Adds new protobuf message HloExecutionProfileData, which describes HloExecutionProfile. PiperOrigin-RevId: 269313040

Backport PR: 39734, add an XLA_FLAGS parameter

Start our own range of IDS.

Rename proto key to not conflict with upstream.

Add AsyncOut support for XLA. This speeds up the multi-gpu training with Horovod by asynchronously triggering the outputs of XLA clusters fed to the HorovodAllreduce nodes. The feature is currently off by default; turn it on by setting TF_XLA_FLAGS="--tf_xla_auto_jit=1 --tf_xla_async_io_level=1". Some data points on 8GPUs on DGX-1, XLA-Async vs. XLA-Sync (i.e., before this commit): 13% perf gain on BERT large pretrain squad fp32, BatchSize=2 7% perf gain on Unet medical trainbench fp32 Design Doc: https://docs.google.com/document/d/1oohJC3BgQYmCb0njAf1Iqd1MShg4cPSeu9ZelnOFY8c/edit Authors: Trent Lo and Ayan Moitra

Merge pull request #35621 from bas-aarts:bas_auto_tune_level PiperOrigin-RevId: 291051983 Change-Id: I9518cca1eb07e44be7857b0c3d87c94de420fdce

change the new parameter name.

[XLA] add the Scatter option to not do atomic operation. This should keep the backward compatibility when this option didn't exist.

Backport PR: 39734, add an XLA_FLAGS parameter

Remove the old tensorflow/compiler/{xla,mlir} directory

Add the new XLA/MLIR directory

Backport tensorflow/core/protobuf/tpu/compile_metadata.proto

Introduce new RngBitGenerator HLO The new instruction has the same signature as xla::BitGeneratorTy what takes a key and a state and returns uniformly distributed random bits and a new value for the state. Its aim is to enable backend specific lowering for the various random bit generator algorithms what should unlock optimization opportunities. PiperOrigin-RevId: 293569472 Change-Id: I4f69d4f9858378fb1241435032ef75657933c056

Adds new protobuf message HloExecutionProfileData, which describes HloExecutionProfile. PiperOrigin-RevId: 269313040

Backport PR: 39734, add an XLA_FLAGS parameter

Start our own range of IDS.

Rename proto key to not conflict with upstream.

Add AsyncOut support for XLA. This speeds up the multi-gpu training with Horovod by asynchronously triggering the outputs of XLA clusters fed to the HorovodAllreduce nodes. The feature is currently off by default; turn it on by setting TF_XLA_FLAGS="--tf_xla_auto_jit=1 --tf_xla_async_io_level=1". Some data points on 8GPUs on DGX-1, XLA-Async vs. XLA-Sync (i.e., before this commit): 13% perf gain on BERT large pretrain squad fp32, BatchSize=2 7% perf gain on Unet medical trainbench fp32 Design Doc: https://docs.google.com/document/d/1oohJC3BgQYmCb0njAf1Iqd1MShg4cPSeu9ZelnOFY8c/edit Authors: Trent Lo and Ayan Moitra

Merge pull request #35621 from bas-aarts:bas_auto_tune_level PiperOrigin-RevId: 291051983 Change-Id: I9518cca1eb07e44be7857b0c3d87c94de420fdce

change the new parameter name.

[XLA] add the Scatter option to not do atomic operation. This should keep the backward compatibility when this option didn't exist.

2020-06-26

Add AsyncOut support for XLA. This speeds up the multi-gpu training with Horovod by asynchronously triggering the outputs of XLA clusters fed to the HorovodAllreduce nodes. The feature is currently off by default; turn it on by setting TF_XLA_FLAGS="--tf_xla_auto_jit=1 --tf_xla_async_io_level=1". Some data points on 8GPUs on DGX-1, XLA-Async vs. XLA-Sync (i.e., before this commit): 13% perf gain on BERT large pretrain squad fp32, BatchSize=2 7% perf gain on Unet medical trainbench fp32 Design Doc: https://docs.google.com/document/d/1oohJC3BgQYmCb0njAf1Iqd1MShg4cPSeu9ZelnOFY8c/edit Authors: Trent Lo and Ayan Moitra

Add AsyncOut support for XLA. This speeds up the multi-gpu training with Horovod by asynchronously triggering the outputs of XLA clusters fed to the HorovodAllreduce nodes. The feature is currently off by default; turn it on by setting TF_XLA_FLAGS="--tf_xla_auto_jit=1 --tf_xla_async_io_level=1". Some data points on 8GPUs on DGX-1, XLA-Async vs. XLA-Sync (i.e., before this commit): 13% perf gain on BERT large pretrain squad fp32, BatchSize=2 7% perf gain on Unet medical trainbench fp32 Design Doc: https://docs.google.com/document/d/1oohJC3BgQYmCb0njAf1Iqd1MShg4cPSeu9ZelnOFY8c/edit Authors: Trent Lo and Ayan Moitra

Merge pull request #35621 from bas-aarts:bas_auto_tune_level PiperOrigin-RevId: 291051983 Change-Id: I9518cca1eb07e44be7857b0c3d87c94de420fdce

change the new parameter name.

[XLA] add the Scatter option to not do atomic operation. This should keep the backward compatibility when this option didn't exist.

2019-08-21

Introduce `indices_are_sorted` attribute for gather/scatter HLO If the attribute is set to `true` then the backend can assume that the gather/scatter indices supplied by the user are sorted what should enable the generation of more efficient code. If the attribute is set to `true` but the indices are not sorted then the behavior is implementation defined. PiperOrigin-RevId: 264574093

2019-08-20

Implementing RFC#126: Allow Op names of the form RepoName>OpName. PiperOrigin-RevId: 264491560

Blacklist convolutions also based on cuBLAS version. PiperOrigin-RevId: 264480644

2019-08-16

Enable equality split for UpdateEnsembleV2. PiperOrigin-RevId: 263835411

Add go headers for config.proto PiperOrigin-RevId: 263674612

Rename the convolution blacklist to a generic name that's not only for convolutions. PiperOrigin-RevId: 263672491

2019-08-15

Avoid blocking SendTensor rpc request. This change includes: 1. Move RemoteSendTensor logic from execute.cc to remote_copy_node.cc and allow calling it in async mode. 2. Use EagerService::Enqueue to handle SendTensor request. This can allow us use streaming enqueue in the future. PiperOrigin-RevId: 263606880

2019-08-13

[XLA:CPU] Add a flag to disable `afn`. PiperOrigin-RevId: 263148244

2019-08-09

Update the TensorInfo protobuf message with an encoding for composite tensors; and update SavedModel to use this new encoding. PiperOrigin-RevId: 262639435

Log cuBLAS version. PiperOrigin-RevId: 262453329

2019-08-08

Added new internal optimization algorithm for embeddings. PiperOrigin-RevId: 262414963

2019-08-07

[TF:XLA] Logging of known cases of performance deficiencies using XLA with Tensorflow. PiperOrigin-RevId: 262104815

2019-08-02

Add a blacklist mechanism for avoiding listed cudnn convolutions. PiperOrigin-RevId: 261392669

Two changes preparing for lazy input tensor copy for remote multi-device functions (make target devices pull remote tensors to avoid redundant copies): - Make master eager service be able to handle requests from remote workers. - Support serializing local TensorHandles and deserializing non-exist RemoteTensorHandles in RemoteMgr. PiperOrigin-RevId: 261382629

Allow to hardcode initial splits for each of the boosted trees. PiperOrigin-RevId: 261332340

Tensor tracer: Adding summary writing capability to tensor tracer. PiperOrigin-RevId: 261213113

2019-08-01

Improve error reporting when loading unknown TypeSpec types. PiperOrigin-RevId: 261201200

2019-07-31

[tfdbg] Improve compatiblity with Grappler - Make tensors from Grappler-created nodes visible to tfdbg. - To this end, add a wildcard node name to the DebugTensorWatch proto. - Add unit test based on tfdbg's filesystem dump mode. - A few unit tests are updated to account for the fact that additional tensors get watched (mainly under GPU tests) with all runtime graph nodes now being watched. PiperOrigin-RevId: 260997920

Merge pull request #30759 from nouiz:give_ptx_code PiperOrigin-RevId: 260917915

2019-07-30

Allow new RPC channels to be assign to new TCP streams instead of sharing a single one. PiperOrigin-RevId: 260726097

Added a flag to ExecutionProfile messages to indicate whether the profile was drawn from a cache. PiperOrigin-RevId: 260623284

2019-07-24

Implement CompositeTensor support in nested_structure_coder.py PiperOrigin-RevId: 259787059

2019-07-22

Add the XLA_FLAGS xla_gpu_ptx_code to allow specifing the PTX code to use.

Fix many of the comments.