package vlsir.circuit

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Signal Concatenation FIXME: documentation of ordering, MSB-LSB

Used in: ConnectionTarget

• repeated ConnectionTarget parts = 1

# Port Connection Pairing between an Instance port (name) and a parent-module ConnectionTarget.

Used in: Instance

• string portname = 1

• optional ConnectionTarget target = 2

# ConnectionTarget Union Enumerates all types that can be (a) Connected to Ports, and (b) Concatenated

Used in: Concat, Connection

• oneof stype

  • string sig = 1

    Reference to `Signal` (name) `sig`

  • Slice slice = 2

    Slice into signals

  • Concat concat = 3

    Concatenation of signals

# Externally Defined Module Primarily for sake of port-ordering, for translation with connect-by-position formats.

Used in: Package

• optional utils.QualifiedName name = 1

  Qualified External Module Name

• string desc = 2

  Description

• repeated Port ports = 3

  Port Definitions Ordered as they will be in order-sensitive formats, such as typical netlist formats.

• repeated Signal signals = 4

  Signal Definitions, limited to those used by external-facing ports.

• repeated utils.Param parameters = 5

  Params

• SpiceType spicetype = 6

  Spice Type, SUBCKT by default

Module Instance

Used in: Module

• string name = 1

  Instance Name

• optional utils.Reference module = 2

  Reference to Module instantiated

• repeated utils.Param parameters = 3

  Parameter Values

• repeated Connection connections = 4

  Port `Connection`s

# Interface Defines the logical IO of a `Module`

Used in: raw.Cell, tetris.Cell

• string name = 1

  Cell Name

• repeated Port ports = 10

  Port List

Module - the primary unit of hardware re-use

Used in: Package, raw.Cell, tetris.Cell

• string name = 1

  Module Name

• repeated Port ports = 2

  Port List, referring to elements of `signals` by name Ordered as they will be in order-sensitive formats, such as typical netlist formats.

• repeated Signal signals = 3

  Signal Definitions, including externally-facing `Port` signals

• repeated Instance instances = 4

  Module Instances

• repeated utils.Param parameters = 5

  Parameters

• repeated string literals = 6

  Literal Contents, e.g. in downstream EDA formats

# Package A Collection of Modules and ExternalModules

Used in: netlist.NetlistInput, spice.SimInput

• string domain = 1

  Domain Name

• repeated Module modules = 2

  `Module` Definitions

• repeated ExternalModule ext_modules = 3

  `ExternalModule` interfaces used by `modules`, and available externally

• string desc = 10

  Description

# Port An externally-visible `Signal` with a `Direction`.

Used in: ExternalModule, Interface, Module

• string signal = 1

  Reference to `Signal` by name

• Port.Direction direction = 2

  Port direction

Used in: Port

• INPUT = 0

• OUTPUT = 1

• INOUT = 2

• NONE = 3

# Signal A named connection element, potentially with non-unit `width`.

Used in: ExternalModule, Module

• string name = 1

  Signal Name

• int64 width = 2

  Bus Width

# Signal Slice Reference to a subset of bits of `signal`. Indices `top` and `bot` are both inclusive, similar to popular HDLs.

Used in: ConnectionTarget

• string signal = 1

  Parent Signal Name

• int64 top = 2

  Top Index

• int64 bot = 3

  Bottom Index

Spice Type, used to identify what a component is in spice

Used in: ExternalModule

• SUBCKT = 0

  The default value is implicitly SUBCKT

• RESISTOR = 1

• CAPACITOR = 2

• INDUCTOR = 3

• MOS = 4

• DIODE = 5

• BIPOLAR = 6

• VSOURCE = 7

• ISOURCE = 8

• VCVS = 9

• VCCS = 10

• CCCS = 11

• CCVS = 12

• TLINE = 13