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• bytes mixer = 1

• repeated Ac97State.BusMaster bus_masters = 2

Used in: Ac97State

• uint32 bdl_address = 1

• uint32 bdl_current_index = 2

• uint32 bdl_last_valid_index = 3

• uint32 status = 4

• uint32 bdl_prefetched_index = 5

• uint32 control = 6

• optional AhciHostState.ControlRegisters control = 1

• repeated AhciHostState.PortState ports = 2

Used in: AhciHostState

• uint32 capabilities = 1

• uint32 global_host_control = 2

• uint32 irq_status = 3

• uint32 ports_implemented = 4

• uint32 version = 5

Used in: PortState

• uint32 command_list_base0 = 1

• uint32 command_list_base1 = 2

• uint32 fis_base0 = 3

• uint32 fis_base1 = 4

• uint32 irq_status = 5

• uint32 irq_mask = 6

• uint32 command = 7

• uint32 task_flie_data = 8

• uint32 signature = 9

• uint32 sata_status = 10

• uint32 sata_control = 11

• uint32 sata_error = 12

• uint32 sata_active = 13

Used in: AhciHostState

• uint32 index = 1

• int32 busy_slot = 2

• bool init_d2h_sent = 3

• optional PortRegisters registers = 4

• uint32 sense_key = 1

• uint32 asc = 2

• uint32 index = 1

• bytes data = 2

• bool nmi_disabled = 3

• uint64 gpa = 1

• uint64 size = 2

• uint32 current_index = 1

• uint32 current_offset = 2

• uint64 dma_address = 3

• repeated HdaDuplexState.Stream streams = 1

Used in: HdaDuplexState

• uint32 id = 1

• uint32 channel = 2

• uint32 format = 3

• uint32 gain_left = 4

• uint32 gain_right = 5

• bool mute_left = 6

• bool mute_right = 7

• uint32 digital_output = 1

• uint32 main_status = 2

• uint32 datarate_select = 3

• uint32 error_status_0 = 4

• uint32 step_rate = 8

• uint32 head_load_time = 9

• uint32 lock = 10

• uint32 config = 11

• bytes fifo = 12

• repeated I82078FdcState.FloppyDrive drives = 13

• uint32 drive_index = 14

Used in: I82078FdcState

• uint32 cylinder = 1

• uint32 head = 2

• uint32 sector = 3

• uint32 perpendicular = 4

• repeated I8257DmaState.I8257DmaController controllers = 1

Used in: I8257DmaController

• uint32 base = 1

• uint32 count = 2

• uint32 page = 3

• uint32 mode = 4

Used in: I8257DmaState

• repeated I8257DmaChannel channels = 1

• uint32 mask = 2

• uint32 flip_flop = 3

• bytes hda_registers = 1

• uint32 rirb_counter = 2

• uint64 wall_clock_counter = 3

• optional Ich9LpcState.Apm apm = 1

Used in: Ich9LpcState

• uint32 control = 1

• uint32 status = 2

• repeated IdeHostState.PortState ports = 1

Used in: PortState

• uint32 command = 1

• uint32 status = 2

• uint32 prdt_address = 3

Used in: IdeHostState

• optional BusMaster bus_master = 1

• repeated TaskFile task_files = 2

• bytes buffer = 3

• uint32 buffer_position = 4

• uint32 control = 5

• uint32 active_tf_index = 6

Used in: PortState

• uint32 feature0 = 1

• uint32 feature1 = 2

• uint32 count0 = 3

• uint32 count1 = 4

• uint32 lba0 = 5

• uint32 lba1 = 6

• uint32 lba2 = 7

• uint32 lba3 = 8

• uint32 lba4 = 9

• uint32 lba5 = 10

• uint32 device = 11

• uint32 command = 12

• uint32 error = 13

• uint32 status = 14

• uint32 control = 15

• sint64 offset = 1

• uint32 bus = 1

• uint32 slot = 2

• uint32 function = 3

• bytes config_space = 4

• repeated PciDeviceState.MsiXTableEntry msix_entries = 5

• bool pcie = 6

Used in: PciDeviceState

• uint64 address = 1

• uint32 data = 2

• uint32 control = 3

• uint32 config_address = 1

(message has no fields)

• optional Piix4PmState.Apm apm = 1

Used in: Piix4PmState

• uint32 control = 1

• uint32 status = 2

• uint32 pm1_status = 1

• uint32 pm1_enable = 2

• uint32 pm1_control = 3

• uint32 pm1_timer = 4

• uint64 gpe0_status = 10

• uint64 gpe0_enable = 11

• uint32 smi_enable = 12

• uint32 smi_status = 13

• uint32 status = 1

• uint32 mode = 2

• optional Ps2State.Keyboard keyboard = 3

• optional Ps2State.Mouse mouse = 4

• uint32 a20_gate = 5

Used in: Ps2State

• uint32 scancode_set = 1

• uint32 leds = 2

Used in: Ps2State

• uint32 buttons = 1

• uint32 dx = 2

• uint32 dy = 3

• uint32 resolution = 4

• uint32 sample_rate = 5

• uint32 scaling = 6

• uint32 stream_mode = 7

• repeated QxlState.GuestSlot guest_slots = 2

• optional QxlState.GuestPrimary guest_primary = 3

• repeated uint64 free_resources = 5

• repeated QxlState.Surface surfaces = 6

• repeated QxlState.Drawable drawbles = 7

Used in: QxlState

• uint64 slot_address = 1

Used in: QxlState

• uint32 width = 1

• uint32 height = 2

• int32 stride = 3

• uint32 format = 4

• uint32 position = 5

• uint32 mouse_mode = 6

• uint32 flags = 7

• uint32 type = 8

• uint64 mem_address = 9

Used in: QxlState

• uint64 mem_start = 1

• uint64 mem_end = 2

• bool active = 3

Used in: QxlState

• uint32 id = 1

• uint64 slot_address = 2

• optional UhciHostState.Operational operational = 1

• repeated UhciHostState.Port ports = 2

Used in: UhciHostState

• uint32 usb_command = 1

• uint32 usb_status = 2

• uint32 usb_interrupt_enable = 3

• uint32 frame_number = 4

• uint32 frame_list_base = 5

• uint32 frame_timing = 6

Used in: UhciHostState

• uint32 status_control = 1

• uint32 configuration_value = 1

• uint32 remote_wakeup = 2

• uint32 device_address = 3

• uint32 version = 1

• uint32 index = 2

• bytes registers = 3

• uint32 mp_state = 1

  KVM Multi-processor state

• bytes regs = 2

  X86 Regs

• bytes sregs = 3

  X86 SRegs

• bytes xsave = 4

  X86 XSAVE

• bytes xcrs = 5

  X86 XCRS

• bytes msrs = 6

  X86 MSRS

• bytes lapic = 7

  X86 LAPIC

• bytes debug_regs = 8

  Debug regs

• bytes nested_state = 9

  Nested states

• bytes events = 10

  KVM Vcpu events

• int64 tsc_khz = 11

  TSC kHz

• bytes fpu = 12

  X86 FPU

• bytes cpuid = 13

  X86 CPUID

• uint32 misc_output = 1

• uint32 status = 2

• uint32 sequencer_index = 3

• bytes sequencer = 4

• uint32 gfx_index = 5

• bytes gfx = 6

• uint32 attribute_index = 7

• bytes attribute = 8

• uint32 crtc_index = 9

• bytes crtc = 10

• uint32 palette_read_index = 11

• uint32 palette_write_index = 12

• bytes palette = 13

• uint32 dac_state = 14

• uint32 feature_control = 15

• uint32 latch = 16

• repeated VirtioConsoleState.Port ports = 1

Used in: VirtioConsoleState

• uint32 id = 1

• bool ready = 2

• optional VirtioPciState.CommonConfig common_config = 1

• repeated VirtioPciState.Queue queues = 2

• uint32 isr_status = 3

Used in: VirtioPciState

• uint64 guest_feature = 4

• uint32 msix_config = 5

• uint32 device_status = 7

• uint32 queue_select = 10

Used in: VirtioPciState

• bool enabled = 1

• int32 msix_vector = 2

• int32 size = 4

• uint32 last_available_index = 5

• uint64 descriptor_table_address = 6

• uint64 available_ring_address = 7

• uint64 used_ring_address = 8

• repeated VirtioVgpuState.VirglContext virgl_contexts = 1

Used in: VirtioVgpuState

• uint32 context_id = 1

• repeated VirglContext.VirglResource virgl_resources = 2

• repeated bytes virgl_cmds = 3

Used in: VirglContext

• uint64 gpa = 1

• uint32 size = 2

• bytes resource_args = 3

• optional XhciHostState.Operational operational = 2

• optional XhciHostState.Runtime runtime = 3

• optional XhciHostState.CommandRing command_ring = 4

• repeated XhciHostState.Port ports = 5

• repeated XhciHostState.Slot slots = 6

• repeated XhciHostState.Interrupt interrupts = 7

Used in: XhciHostState

• uint32 dequeue = 1

• bool consumer_cycle_bit = 2

Used in: XhciHostState

• uint32 management = 1

• uint32 moderation = 2

• uint32 event_ring_table_size = 3

• uint64 event_ring_table_base = 4

• uint64 event_ring_dequeue_pointer = 5

• uint64 event_ring_segment_start = 6

• uint32 event_ring_segment_size = 7

• uint64 event_ring_enqueue_index = 8

• bool event_ring_producer_cycle_bit = 9

Used in: XhciHostState

• uint32 usb_command = 1

• uint32 usb_status = 2

• uint32 device_notification_control = 3

• uint64 command_ring_control = 4

• uint64 context_base_array_pointer = 5

• uint32 configure = 6

Used in: XhciHostState

• uint32 status_control = 1

Used in: XhciHostState

• uint32 microframe_index = 1

Used in: XhciHostState

• bool enabled = 1

• bool addressed = 2