Add support to GEM5 full-sytem simulation.
Sheng Xu, Xiaoming Chen, Yinhe Han (HomePage) , Xuehai Qian(University of Southern California)
This program is currently maintaind by Liang Yan (yanliang405@gmail.com) .
Control Computing Laboratory, State Key Laboratory of Computer Architecture, ICT, CAS.
Buddy-ram: Improving the performance and efficiency of bulk bitwise operations using DRAM (MICRO 17)
Accelerating Pointer Chasing in 3D-Stacked Memory: Challenges, Mechanisms, Evaluation (ICCD 2016)
LazyPIM: An Efficient Cache Coherence Mechanism for Processing-in-Memory (CAL 2016)
PIM-Enabled Instructions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture (ISCA 15)
A scalable processing-in-memory accelerator for parallel graph processing (ISCA 15)
Data-reorganization: Data Reorganization in Memory Using 3D-stacked DRAM (ISCA 2015)
Practical Near-Data Processing for In-memory Analytics Frameworks (PACT 2015)
NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules (HPCA 2015)
TOP-PIM: Throughput-Oriented Programmable Processing in Memory (HPDC, 2014)
RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization (MICRO 2013)
ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing (DAC 15)