Proto commits in BerkeleyHCI/PolymorphicBlocks

These 58 commits are when the Protocol Buffers files have changed:

2026-06-07

IoT fan + led driver combo, new parts, I2C controller bridge (#518) Refactors the IoT fan driver example to be a combination fan driver / 12v-capable neopixel driver. Changes it to a two-level board, adds sensors and the choice of USB PD input. Layout to be completed as a separate PR, which may also require changing the pinning and circuit split between levels. Removes IoT knob example, which is now redundant. Component library changes: - Add optional resistance to I2cPullup - Add I2cController bridge, allow I2cController to have addresses (mostly to encode inner devices), with tests - Add OE pin to 74xx1g125 - Add VL53L5CX Core / compiler changes: - Add array concatenation operation to compiler, using addition op - Add tolerance-shrinking subtract to compiler, though not plumbed through to frontend yet - Regenerate proto

The documentation is generated from this commit.

2026-05-17

Sub-board infrastructure with export-tap (#486) Adds a SubblockBoard and WrapperSubblockBoard Block subclasses which have their internal implementation (links and blocks) in a separate board (or in the Wrapper case, discarded - the internal implementation is for electronics modeling only). Blocks marked as external can be used for, for example, connectors that sit on the carrier board. Implementation-wise, this adds an export-tap construct, an export (or export-array) construct that does not propagate parameters but can be hooked onto exterior ports that have other exports (including export-taps). A compiler check pass checks that inner ports do not have defined parameters (are empty) and (in the array case) elements are equal. Refactors A4988 and VL53L0x connectors to use this new infrastructure instead of the older WrapperFootprintBlock. which is removed. Infrastructure towards #367, #389 Future PRs will: - Implement multi-netlist generation - Implement connector pairs with some examples - Refactor microcontrollers to use this infrastructure

2026-05-10

Add explicit fallback to array reduction; add error value (#485) Changes the IR and compiler to define the empty array output of array reduction operations in the frontend, allowing better type propagation (especially disambiguating float 0 and range 0 for sums). Changes the error handling to generate an error value instead of crashing the compiler, allowing a partial compile instead of a unhelpful stack trace. In the compiler, moves the param errors into the param value, while tracking overassigns separately because of the immutability of the param value system. Also tightens up what reduction operations are allowed in the array subtypes. Resolves #223

2026-04-26

Export compiled design tree as a JSON (#482) Exports the compiled design tree as a JSON, including connectivity and parameter value data. Useful for getting compiled design information when not using the IDE, and perhaps in the future as a easier to use feature than the proto definitions. Meant to be human-usable. Defines the JSON structure using Pydantic. Does some regex-based postprocessing to condense range values and params. Adds a functional TransformUtil that makes this easier. Eventually, the other TransformUtil users may be refactored to use this. Refactors the compiler to track the link-side port and include the block-side port <-> link side port data in the compiled result. This is done by storing the port suffix with the link path. Also fixes range equality for empty ranges.

2026-03-30

Reverse power flows, unified battery charging port (#462) Resolves #330. Adds a reverse voltage direction for VoltageSource/Sink. Only at most one reverse voltage source per connection (and combined with the unique forward VoltageSource requirement, means at most one bidirectional power path). Adds unit tests. Refactors the LiPo connector, Mcp73831 battery charger IC, and reverse-capable PMOS reverse voltage protector to use this new infrastructure and eliminates the dedicated charging pseudo-port. This refactors the voltage DummyDevices to the electronics_model to support unit tests. The other ones should eventually be migrated To check for reverse source uniqueness, this adds some code infrastructure: - Adds an array-element equals for RangeExpr only - Adds bool array NOT operation - Adds compiler unit tests - Regenerates protos, bumps proto version.

2026-03-15

Unify Port and Bundle by merging Bundle functionality into Ports (#453) On the path to compositional passive. Also simplifies a bunch of code. Refactors the libraries to use Port instead of Bundle, but retains Bundle with a deprecation warning. Changes Bundle.with_elt_initializers to be private. It is an API with only one consumer in the pinmap util and a better solution will need to be found for it. Updates the proto version.

2025-04-08

Add shrink-multiply op to backend (#402) Add the tolerance-shrinking multiply operation to the backend, so it can be done without generators which were constraining in terms of parameter dataflow and syntactic boilerplate. Renames the previous cancel_multiply (which was a bit too implementation-focused) to shrink_multiply (which is more use-case focused). Also better documentation in terms of target tolerance and contributing tolerance. Netlists should be the same, but there are ordering changes from changed order of parts. Resolves #393

2024-04-24

Structured errors from compiler (#342) Instead of errors as one monolithic string from the compiler, it's now structured with separate path, kind, name, and detail components. Also adds `edgir.local_path_to_str_list` utility function. Updates proto version to 4.

2023-08-29

Expand connections in sub-expressions and preserve original expressions (#285) Infrastructure for a larger feature, this preserves the original connect expressions instead of lowering them in-place (as is prior behavior), instead adding the lowered expressions to a expanded field in the connect expression. This keeps the connect implementation the same and should not functionally change anything. Though with the new expanded field, it's apparent that the previous implementation was pretty messy and made heavy use of mutable state. Eventually, that should be fixed / totally refactored and overhauled, but this isn't the time and place for it. That might better track when a connect can be fully expanded, instead of incrementally mutating the connect and hoping that it all works out at the end. In particular, there's multiple overlapping meanings for intermediate expanded values in connectArray. Empty expanded could mean an empty connect, or it hasn't been expanded. Single expanded could mean it expanded into one connection, or a substitution was done on the collective array connect, and still needs to be expanded into multiple individual connects. In the future, these should be explicitly tracked in the compiler. This changes the IR in a way that breaks compatibility. Also some simplification of internal compiler structures.

2023-08-21

wip

wip preserve original connect form

2023-06-28

Interface Mixins (#263) Infrastructural support for interface mixins - that is, the ability to add additional properties to an abstract block, e.g. `RotaryEncoder` with `HasSwitch`. Interface mixins can only be used on abstract classes, concrete classes may only be one class (but may implement multiple mixins, e.g. a single device can implement `RotaryEncoder` with `HasSwitch`) In the Python HDL frontend, interface mixins are defined as a class. It does not inherit its base class, instead it declares its base class as a type parameterization. This is added into the superclass list on the proto. It's a bit inelegant structurally, but it allows the type checker and autocomplete to see the mixin fields only. In the compiler, when it sees a unrefined mixin, the contents of the mixins are appended onto the (abstract) base class. This is only to support visualization - this will always produce an error, and the process may be unpredictable. Ultimately, it needs to be refined into a single use-defined concrete class, with the system checking for proper subclass relations. On the proto side, this changes `BlockLike`'s `lib_elem` to also have optional mixins as library references. Pre-refinement mixins are also stored in `HierarchyBlock` Future PRs will refactor some existing library elements to use mixins, and will likely also need to improve on the infrastructure. Examples: - `IoController` with `HasI2s` (maybe even `HasCan`, `HasUsb`?) - `IoController` with `HasPowerSource`, `HasUsbPowerSource` - `VoltageRegulator` with `HasEnable` Other refactoring: - Adds `super_superclasses` to all elem proto types, which defines non-immediate superclasses. This enables refinement / superclass checks to not need the full library and can operate solely on the design tree. - Refactor the compiler to use these (where available, post-elaboration) instead of relying on library inheritance analysis. Pre-elaboration, the entire self-class+superclasses list are passed in - Move subclass validation into DesignStructuralValidate - one step closer to eliminating stateful compiler errors (#223) - Rename block_class -> self_class for consistency with other protos - (unit testing) ElemBuilder add support for library composition - Move scalafmt config into the compiler/ directory so it can be invoked from sbt Potential future work: - How can multiple mixins compose? e.g. what if IoController HasPowerSource and HasUsbPowerSource both have a ground? Resolves #104

2023-04-27

Python packaging defs (#247) - Add pyproject.toml - Refactor paths for packaging: - precompiled compiler now in edg_core/resources - HDL interface server in its own package, to be runnable with `python -m` - Update documentation - Package uploaded to pip

2023-03-20

Directed refinement (#236) Refinements can now be a ParamValue of another parameter, instead of only explicit values. This allows some deduplication and allowing a single value to drive multiple parameters, useful for multi-channel designs.

2023-03-01

Block-based default subclass refinement and ideal components (#220) Add a default refinement on blocks through the decorator `@abstract_block_default(lambda: MyRefinedBlock)`, and add default ideal refinements for power converters and IoController. This allows designs with unselected choices of those components to build (instead of the cascading errors with an abstract part with no implementation). Ideal components create an error by default if they are left in the design. Changes the DigitalLink behavior to apply tolerance thresholds loosely - previously the IO voltage threshold was the overly-strict (gnd.upper - tol, pwr.lower + tol), now this is the less-strict (gnd.lower - tol, pwr.upper + tol). This means no false positives (where working designs may be flagged), but potential false negatives (where broken designs may not be flagged). A tight tolerance probably requires some level of symbolic analysis, see #187 Other infrastructural cleanups: - Modify implementation of properties like `@abstract_block` to use objects instead of strings, to be more friendly to static analysis tools. Add type annotations to `_elt_properties`. - Docs for some decorators - Clean up and unify dummy blocks (eg DummyVoltageSource), also make some link parameters available in the dummy block

2022-12-06

Separate refdesing from netlisting, refinement-pass infrastructure (#178) ... allowing the refdes to be visible as a parameter, eg for the IDE tree view and future PDFing. This introduces a new HDL-interface construct (with corresponding proto), a refinement pass that takes a design and a list of existing solved values, and returns new solved values (here, the refdes) Other minor refactorings: - In unit tests, prefer NetlistBackend (instead of NetlistTransform), at least where we aren't examining the intermediate output - DRY out the netlisting code in some unit tests in NetlistTestCase.generate_net

Order map elements in proto (#175) Changes the proto from `map<string, V>` to use `repeated` of `(name, V)` sub-messages. Resolves #113 Implementation notes: - In Scala, this defines an implicit .toPb on SeqMap[Str, ElemType], and an implicit .toSeqMap (when a SeqMap specifically is needed) and .asPairs (to compose with Seq methods) on Seq[ProtoType] (for the name/value pair sub-messages). - Proto construction utils use ordered SeqMap instead of unordered Map, - In Python, add a edgir.add_pair (to add a NamedPair with specified name to the repeated field, returning the value to be populated) util, since Python unfortunately does not support nice-looking implicits. - Also add a edgir.pair_get_opt (for a list of NamedPair, return the one of specified type or None) and .pair_get (requires the index exists) - Lots of updating test code. - Eliminate naming order metadata (obsoleted). - Refactor frontend to not generate metadata field at all if there is no metadata. - Frontend internals: change ordering in which constraints are generated, required connects then port inits then param inits. - Refactor FootprintBlock to use fp_pinning param instead of metadata, as part of a general effort to clean up metadata. - Remove footprint proto test, in favor of just keeping the footprint to netlister test instead of testing internal details. Also the array literal test isn't straightforward =( - Delete some no-longer-used metadata. Future refactorings: - Refdes annotation transform, separate from netlister - Ensure netlister is deterministic - Eliminate usage of metadata for netlist-related data, instead using param and the type hierarchy

2022-12-04

plumb toggles from DesignTopConfig to NetlistGenerator (#177) Added an argument list as a map<string, string> to hdl.proto. Generated new proto files to reflect the change. Plumbed argument list containing RefdesMode from protobuf to NetlistGenerator. Set the default value of RefdesMode to pathName. Added checks for invalid keys in arguments list. Co-authored-by: Richard Lin <richard.lin@berkeley.edu>

2022-09-21

Concatenate operator (#149) Adds FLATTEN (for arrays-of-arrays) and CONCATENATE (text append) operators in the IR. The implementation is minimal to support these two use cases: - Check I2C addresses - flatten the address list of all attached devices, then check for uniqueness - Refactor array-connect expansion to use the expression language internally, instead of custom compiler tasks that basically do the same thing. Other minor maintenance fixes: - Roll Scala version for compiler - Add .jvmopts so sbt doesn't barf on startup Other changes: - Support .flatten(port => contained array parameter) on array ports - Support EQ and NEQ between Array types - Significant cleanup of ArrayExpr, deduplicating a lot of stuff that used to live in each subclass into infrastructure - Changes array generation in frontend to use the ValueExpr.Array construct instead of the more restrictive array literals - Refactors allocate naming to include the hierarchical path for connected arrays, instead of just assigning the next number - Unit tests for I2C links testing the above featurre - This new style of tests uses the expression language's assertions, instead of separate checks in the toplevel testdriver

2022-08-15

Stateless HDL Interface (#135)

2022-08-11

Support running backends (eg, netlister) from the HdlInterfaceServer (#134)

2022-08-04

Design tooltip generator (#125) * Works with Hard-coded description Update: I finally figured out how to successfully send a hardcoded array of different data types through protobuf and interpret it in Scala. * Works with User-Defined String Description Added a description field with a default value in the BaseBlock class in Blocks.py. User can now define description strings in the IDE, but the access to variables still needs to be implemented. * Replaced old tooltip code with new system * Cleaned up library description code + added bolds * Update HierarchyBlock.py * Update edg_core/Blocks.py Co-authored-by: Richard Lin <richard.lin@berkeley.edu> * Update edg_core/Blocks.py Co-authored-by: Richard Lin <richard.lin@berkeley.edu> * Stylistic fixes * Create test_block_description.py * Update blinky_skeleton.py * Updated to include descriptions for Links * Started on tooltips with mypy type checking * Updated to work with static typing structure * Fixed mypy typing errors * Update test_block_description.py * Update edg_core/Blocks.py Co-authored-by: Richard Lin <richard.lin@berkeley.edu> * Minor Cleanups * Move StringDescriptionElement outside Co-authored-by: Richard Lin <richard.lin@berkeley.edu>

2022-06-11

Multipack support (#116)

2022-04-19

Array-valued expr support through frontend (#110)

2022-04-07

Abstract microcontroller type (#107)

2022-04-01

Block-side port arrays (#105)

2022-02-18

Single-shot generators and compiler refactor (#96)

2021-12-22

PR 72/89 consistency updates (#90)

2021-09-27

Replace gRPC with stdin/stdout; remove module reload in Python (#40)

2021-09-01

Add hull operator, remove min(array[range]) -> float (#39)

2021-05-17

add lack of semantics

Add superclasses for links, ports, and bundles

2021-05-12

Add self_class to proto, update rest of code to use self_class where appropriate (#35)

2021-04-17

Core refactor and Scala compiler (#32)

2021-03-27

refactor Electrical* -> Voltage*

2021-02-21

return design on nonfatal errors

2021-02-15

wip refactorign the importer, broken

wip refactoring generators meta

2021-02-12

pipe through generator errors

2021-02-11

implement length including in compiler

update proto to support refinements + Scala consistency

2021-02-08

discard cache RPC and implementation

2021-02-04

refinements plumbing in proto

refinements scaffolding

2021-02-03

infra for refinements

2021-02-01

generate error + meta merging

2021-01-31

wip

wip

2021-01-29

grpc compiler + persistence + refactor

2021-01-28

wip infra to pass constprop results

2021-01-27

wip

wip

2021-01-25

fix python grpc compilation

wip

grpc beginnings

Define message structs for currently used metadata defs (#24)

2020-12-31

IR support for directed constraints and link arrays (#21)

2020-10-16

Code by the UIST'20 paper deadline State of the system during the UIST'20 review cycle, and for the user studies (well, at least at the end, code was updated regularly during the studies).