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* not allowed w/in the library
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Parameters that must be defined for the generator to fire. These parameters are the only ones accessible to the generator.
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Refinements may introduce new parameters which would not be assigned a value in the parent class. In those cases, those new parameters are given these default values.
unordered
* Bridges, which adapt an edge port to a link port - eg, edge VoltageSink to an internal link VoltageSource, are defined as blocks in the IR. Upper layers can define convenience constructs and/or infer these blocks.
* Connections between internal block and link ports are represented by connected constraints. Connections between internal; block and edge (of this block) ports are represented by exported constraints.
self class, equivalent to the library name
immediate superclasses, may be empty
all (recursive) superclasses above superclasses
class pre-refinement, only defined if refined
mixins pre-refinement, from library elem
optional, and removed upon invocation
true if self_class is abstract, and should error if used in a design
optional default refinement subclass, only valid for library blocks
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superclasses, may be empty
all (recursive) superclasses above superclasses
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The class that applies to every link in the set/array. Used when a new link is instantiated by the front or back end.
Only designs should contain an implementation here
the last index is the index of the link, the first indices (if any) are the indices of the corresponding port in the inner link
includes all exported constraints to map link ports to my ports
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* not allowed w/in the library
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These are essentially a element in a map<string, value>, but because maps are unordered (whereas we want to preserve ordering to preserve design intent through the compiler), we use a sequence of these pairs.
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superclasses, may be empty
all (recursive) superclasses above superclasses
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The class that applies to every port in the set/array. Used when a new port is instantiated by the front or back end.
Library blocks may define ports (if fixed number of ports) or not (for generators or abstract blocks). A valid design must define ports, but the ports may be empty.
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* Wrapper for different port like elements
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* 'port' disallowed w/in the library
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